| 摘要 |
PURPOSE:To suppress jitter without deteriorating the clock extracting sensitivity by limiting the reset of an N-adic counter by an external input for a prescribed period after the N-adic counter generates a carry pulse. CONSTITUTION:A clock of an oscillator 2 is fed to the N-adic counter 4 to output the 1st pulse 111 for carry, the 1st pulse 111 is fed to the 1st shift register 14 to output the 2nd pulse 113, the 2nd pulse 113 is fed to the 2nd shift register 15 to output the 3rd pulse and the 1st pulse 111 and the 3rd pulse are fed respectively to the set and reset terminals of an FF 16. Further, an edge detection circuit 3 detects an edge of the input pulse to output the 4th pulse 114, an AND gate 17 ANDs an inverted output of the FF 16 and an output of the edge detection circuit 3, an OR gate 5 ORs the output of the AND gate 17 and the 2nd pulse 113 to generate the 5th pulse 115, which resets the N-adic counter 4 to output the 5th pulse 115. |
