发明名称 MANUFACTURE OF STACKED CMOS FET
摘要 PURPOSE:To form a gate electrode and a source and drain of the second layer FET in self-alignment by a method wherein an insulation film containing an impurity is selectively formed on the region other than a gate electrode and the impurity is diffused into the second silicon layer, using the insulation layer as an impurity diffusion source. CONSTITUTION:On a semiconductor substrate 201, an impurity layer 204 with a conductive type opposite to that of the substrate, a gate insulation film 202 and a gate electrode 203 made of polycrystalline silicon are formed. An insulation film 205, which is not doped with an impurity, is deposited at least on the surface of the gate electrode 203. Then an insulation film 206, which is doped with the impurity with the same conductive type as that of the substrate 201, is formed over the whole surface to the thickness at least the same as the thickness of the gate electrode 203. A photoresist 207 is applied over the whole surface of the insulation film 206 and the top surface of the gate electrode 203 is exposed. Then, a thermal oxidization is carried out and an insulation film 208 is formed on the top surface of the gate electrode 203 and a single crystal layer 209 is formed over the whole surface. Finally, the impurity is diffused from the insulation layer 206 by annealing at the temperature 800 deg.C or higher and source and drain impurity diffused layers 210 of the second layer FET are formed.
申请公布号 JPS61248461(A) 申请公布日期 1986.11.05
申请号 JP19850089317 申请日期 1985.04.25
申请人 NEC CORP 发明人 ABIKO HITOSHI
分类号 H01L27/092;H01L21/20;H01L21/8238;H01L27/06;H01L29/78;H01L29/786 主分类号 H01L27/092
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