发明名称
摘要 PURPOSE:To secure variation for only the phase characteristics with the flat transmission amplitude characteristics by forming the circuit with the integrator, the attenuator and the adder/subtractor each. CONSTITUTION:The output signal of attenuator 5 is subtracted at subtractor 6 and via the input signal applied to input terminal IN to obtain the 1st signal. The 1st signal is supplied to integrator 1 and then amplified through amplifier 3 after integration. Then the 1st signal is subtracted from the output signal of amplifier 3 through subtractor 7 to obtain the 2nd signal. And the 2nd signal is supplied to integrator 2 and then amplified through amplifier 4 after integration. Then the 2nd signal is subtracted from the output signal of amplifier 4 through subtractor 8 to obtain the 3rd signal. An addition is then given between the 3rd signal and the input signal to obtain the 4th signal through adder 10, and the 4th signal is supplied to attenuator 5. Then an addition is given between the output signal of attenuator 5 and the 4th signal through adder 11 to obtain the 5th signal, and then the intput signal is subtracted from the 5th signal via subtractor 9 to obtain the output signal from output terminal OUT. In such way, the transmission amplitude characteristics always features flatness without the gain, and at the same time the monotonous reduction is secured for the phase from 0 deg.--360 deg..
申请公布号 JPS6150535(B2) 申请公布日期 1986.11.05
申请号 JP19780143186 申请日期 1978.11.20
申请人 TORIO KK 发明人 ASAHI NOBUMITSU
分类号 H03H7/01;H03H7/20;H03H11/20;H04B3/04 主分类号 H03H7/01
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