| 摘要 |
PURPOSE:To obtain a high performance heterojunction FET, by sequentially laminating non-added GaAs having a broad band gap and n-GaAlAs through a p-GaAS layer on a semi-insulating GaAs. CONSTITUTION:A p-GaAs layer 2 is held between a semi-insulating GaAs substrate 1 and an undoped i-GaAs layer 3. Therefore, a barrier DELTAE is generated between the substrate 1 and the channel layer 3. When the concentration of the p-type layer 2 is 1X10<19>/cm<3>, DELTAE 0.7eV is obtained. The barrier prevents the intrusion of a large amount of electrons in the substrate in order to compensate for the decrease in electron density in a drain beneath a gate electrode 6 when a drain voltage exceeding a drain-current saturated state is applied. The barrier also limits the current to the channel 3 and substantially reduces the electron velocity component in the vertical direction with respect to the substrate. As a result the component in parallel with the substrate is increased, and the saturation value and gm of the drain current are increased. The degree of increase depends on the thickness of the layer 3, the height of DELTAE and the length of the gate. When the band gap of the layer 2 is larger than the layer 3, the higher effect can be obtained. |
