发明名称 |
FIFO SELF-DIAGNOSING DEVICE |
摘要 |
PURPOSE:To make it possible to make operation check by the operation of only one CPU in a multi-CPU system suing an FIFO by providing newly a bus interface section and a spurious control signal generating section. CONSTITUTION:By outputting data to be transferred to a CPU to DBUS 1 and generating a WR signal to FIFO 3, data on the DBUS 1 are stored in FIFO 3. The data bus of the CPU 2 and controlling signal are separated from FIFO in a bus interface section 5 and made to high impedance state. A spurious READ signal TR is generated in FIFO from a spurious control signal generating section 6 provided in the CPU 1, and data stored in FIFO are outputted to a DBUS 3. A spurious WRITE signal TW is generated from the spurious control signal generating section to FIFO 4, and data on the DBUS 3 are stored in FIFO 4. An RL signal is generated to FIFO 4 and the operation check of FIFO is completed by comparing read data by the CPU 1 with the data outputted first from the CPU 1 to FIFO 3. |
申请公布号 |
JPS61248141(A) |
申请公布日期 |
1986.11.05 |
申请号 |
JP19850090062 |
申请日期 |
1985.04.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YUASA SACHIHIRO;MIYAZAKI JUN;NISHIDA HIDEJI |
分类号 |
G06F11/22;G06F11/16;G06F12/16 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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