发明名称 INPUT PRECEDENCE CONTROL SYSTEM
摘要 PURPOSE:To shorten 9 time for processing input and output by transferring input data required by a program from an external storage unit to a main memory by prefetched processing of instruction execution of a program and placing it at higher rank of memory hierarchy. CONSTITUTION:A prefetched input controlling section (device) 4 that analyzes an instruction (n) step ahead of present instruction word of a program under execution is provided separately from the instruction execution controlling section of a CPU (central processing unit) 2. By detection of an input instruction (or instruction that calls input processing module) in an input/output precedence controlling section, data are transferred (in unit of block or track) to a main memory, which is high-order of memory hiararchy, from the file of an external memory before the file (assemblage of data) is accessed by the program actually. Thus, the time required for data transfer can be shortened.
申请公布号 JPS61248124(A) 申请公布日期 1986.11.05
申请号 JP19850088518 申请日期 1985.04.26
申请人 HITACHI LTD 发明人 SEKI TAKAAKI;KITAJIMA HIROYUKI;YAMAMOTO AKIRA;KURANO AKIRA
分类号 G06F3/06;G06F12/00;G06F12/08 主分类号 G06F3/06
代理机构 代理人
主权项
地址