| 摘要 |
PURPOSE:To decrease the time when pattern data is shifted and outputted by providing a register inputted with parallel pattern data, two ROMs having a program setting an output after shifting and an OR circuit. CONSTITUTION:Parallel pattern data (a) is inputted to a register 2 and a ROM 3 and the output pattern data of the register 2 is inputted to a ROM 1. In inputting a consecutive pattern data sequentially to the register 2 and a ROM 3 synchronously with a clock signal CL, the pattern data before one point of time in the ROM 3 is inputted to the ROM 1. Data (e) designating the pattern data and the shift bit number inputted to the ROMs 1, 2 is an address data of the ROMs 1, 3 and the output pattern data (c, b) corresponding to the address data are outputted. The output pattern data (c, b) of the ROMs 1, 3 are ORed by OR circuits 4a-4h and outputted as the output pattern data (d).
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