| 摘要 |
PURPOSE:To obtain the titled device operating address generation for horizontal time axis converting processing of a data sampled in high speed while using a low speed clock and suitable for handling the data in a high frequency rate by generating an address at a low speed in a vertical blanking period, writing it in a memory and applying high speed read when the video period starts. CONSTITUTION:A clock I produced from a clock generating circuit 12 is a clock in a sampling frequency, corresponds to a picture element of an input data, uses a 1/16 counter 13 to decrease the frequency to 1/16 to form a clock II, the result is inputted to a reference counter 7, a register 5, an address genera tor 8 and a speed conversion memory 11, and an SH being a ratio of the picture element of the original sample to after reduction (or magnification) is added by SIGMASH circuits 4, 5, the result is compared with the output of the reference counter 7, and when the value is equal, the address of the address generator 8 is revised. Then an output of a synchronous separation circuit 14 is obtained and it is written in the speed conversion memory 11 at a low speed while forming an address during the vertical blanking period.
|
