发明名称 PHASE LOCKED OSCILLATOR
摘要 PURPOSE:To form a phase locked oscillator by only one phase locking by adding a frequency divider and an initial value setting circuit to one phase locked oscillating circuit loop. CONSTITUTION:A phase locked oscillating circuit loop is formed by a phase comparator 2, a VCO3, and frequency dividers 4, 5, and a signal of a frequency f1 and a signal of a frequency f3 are obtained from the frequency divider 4 and the frequency divider 5, respectively. Subsequently, a signal of a frequency f0 is applied to a frequency divider 6 from the VCO3, and a signal of a frequency f2 is obtained. In this case, coincidence in phase between f0, f1 and f3 is not performed directly by an output of the frequency divider 6, therefore, initializing is executed by a signal of a frequency f4 from an initial value setting circuit 7. This setting circuit 7 receives a signal of the frequency f3 being an output of the frequency divider 5 and outputs an initial value setting signal. In this way, a signal phase of each frequency coincides. Accordingly, a phase locked oscillator can be formed by only one phase locking.
申请公布号 JPS60197015(A) 申请公布日期 1985.10.05
申请号 JP19840053764 申请日期 1984.03.21
申请人 NIPPON DENKI KK 发明人 HIRAIDE SATOSHI
分类号 H03L7/08;H03L7/183;H04L7/033 主分类号 H03L7/08
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