发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PURPOSE:To form a delay element having a comparatively large delay time with a small number of circuit elements by using the resistance and the gate capacity of an MOS field effect transistor FET set previously into a basic cell to constitute a delay element. CONSTITUTION:A basic cell 1A contains an inverter INV1 using MOSFETs M1-M4; while a basic cell 1B contains an inverter INV2 using MOSFETs M1-M6. The gate capacities of MOSFETs M2-M6 within the cell 1A are connected in parallel with each other for production of a large capacity Ct. Then a CR type charging/discharging circuit is formed with the capacity Ct and resistances R1 and R2 in both cells 1A and 1B respectively. This charging/ discharging circuit is provided to a signal transmission path between both inverters INV1 and INV2 for formation of a delay element. |
申请公布号 |
JPS61245624(A) |
申请公布日期 |
1986.10.31 |
申请号 |
JP19850086372 |
申请日期 |
1985.04.24 |
申请人 |
HITACHI LTD |
发明人 |
SHIBATA MANABU;URAGAMI KEN;KATONO SHINJI |
分类号 |
H03K19/173;H03K5/00;H03K5/13 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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