发明名称 DECODING SYSTEM FOR ERROR CORRECTION CODE
摘要 PURPOSE:To increase the ability in error correction and to simplify the ability in signal processing and reduce the size of a device by utilizing analog information that a received signal has in addition to syndrome information. CONSTITUTION:The received signal inputted from an input terminal 9 is converted by a binary coding circuit 10 and a ternary coding circuit 11 into a binary and a ternary signal. A nine-bit binary sequence which constitutes an error correction block is parity-checked by a parity checking circuit 13, which outputs a signal '0' to a correcting circuit 15 when there is no parity error or a signal '1' when a parity error is found. A decision circuit 14 receives the ternary signal from the ternary coding circuit 11 and outputs '0' when the signal '0' or '1', or '1' when the signal is an absence bit 'e'. A gate circuit 16 discriminates that an error is correctable or that an error is detected, so its output is used for signal processing. Thus, the ability in error correction is increased and the signal processing is facilitated, so the size of the device is reducible.
申请公布号 JPS61244132(A) 申请公布日期 1986.10.30
申请号 JP19850086796 申请日期 1985.04.23
申请人 HITACHI LTD 发明人 DOI NOBUKAZU;IZUMIDA MORIJI;MITA SEIICHI
分类号 H03M13/00 主分类号 H03M13/00
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