| 摘要 |
PURPOSE:To reduce the burden of a CPU by storing interrupt signals in an address register and selecting and outputting the signal having the highest priority level from the output and processing the interruption having the low degree of urgency. CONSTITUTION:Interrupt signals are inputted to an encoder 100 through interrupt signal lines 1 and are converted to addresses in a register file 102 corresponding to classifications of interrupt. These addresses are stored in an address register 101 and register values corresponding to interruptions are outputted from the file 102. The output of this register is inputted to AND gates 103-105 and their outputs are sent to signal registers 3-5 and bit states for preceding turn-on of individual registers are preserved and OR is operated on signal registers when another interrupt occurs. The value of the signal register of a present executing process is selected from outputs by a selector 7 and the bit having the highest priority level is selected and outputted by a priority level selecting and conversion unit 201.
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