发明名称 TIME SWITCH
摘要 PURPOSE:To provide functions for speed conversion, multiplexing and multi- distribution of multi-dimensional information as well as the replacement of time slots by unifying specific two time switches systematically. CONSTITUTION:Highway 101-104 are time division highways in which a 8-bit parallel signal is 1024-multipled. For 8, 16, or 32kb/s of a low speed signal, an input highway 101 employs 64kb/s universal type with its bits repeated in a time slot. An output highway 104 is the veer multiple highway in which several low speed signals of less than 32kb/s for same destination are multiplexed in a same time slot. Channel memory SPM 2 and 3 are random access memory for which the word length is 8 bits and the number of words is 1024.
申请公布号 JPS61242193(A) 申请公布日期 1986.10.28
申请号 JP19850082441 申请日期 1985.04.19
申请人 HITACHI LTD 发明人 TAKEMURA TETSUO;GOHARA SHINOBU;HORIKI AKIRA
分类号 H04Q3/52 主分类号 H04Q3/52
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