| 摘要 |
PURPOSE:To prevent malfunction at the time of power-on operation and to realize one-chip formation in IC-implementation by providing a counter which outputs an operation signal for activating an output circuit when a clock pulse reaches a specific value and stopping inputting the clock pulse to the counter when the counter outputs the operation signal. CONSTITUTION:When the reset output terminal Q of a flip-flop circuit 14d falls to a low level, a AND circuit 13 inhibits the clock pulse P1c from passing, thereby stopping inputting the clock pulse P1c to the counter 14. The counter 14, therefore, stops counting and outputs an operation signal S14 continuously. Consequently, the output circuit is inactivated until a constant time Ta+Tb is elapsed from the power-on operation. Therefore, even if a light receiving circuit 7 outputs a detection signal S7 by mistake in a stable state right after the power-on operation, the output circuit 8 does not output an output signal S8, so the malfunction is prevented.
|
