| 摘要 |
PURPOSE:To improve the using efficiency of buses by adding a bus cycle control circuit which controls the bus using right at every unit time and a bus arbiter circuit which controls successively the bus using rights given from the bus master and slave parts. CONSTITUTION:A bus slave 21 monitors the information on an address bus 40 and extracts the write data on a data bus 41 and the information on a master discriminating signal 42 to start a writing action after detecting that the slave 21 itself is selected. When the writing action is through, the slave 21 turns on a bus using request signal 36 to the bus arbiter circuit 3 and then turns off the signal 36 after detecting the signal 36 turned on. Then the slave 21 delivers the information showing a bus master 11 to the signal 42 for a period equal to a clock synchronizing with a bus clock signal 31. The master 11 monitors the signal 42 and releases the waiting state as an answer given from the slave 21 after detecting its own discriminating information to finish the relevant cycle. This improves greatly the bus using efficiency.
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