发明名称 INTERRUPTION RELEASING SYSTEM FOR REGISTER
摘要 PURPOSE:To release smoothly and quickly the interruption to a register by providing selection control part for the selection of a single bit and a bit resetting part for the transmission of a clear signal to the selected bit to the register and then releasing the interruption after all bits are turned off. CONSTITUTION:When '1' is set at a certain bit of a register 15, the '1' signal is detected by an OR gate 16 and the signal IRQ is transmitted to a processor. The highest flip-flop is detected out of those flip-flops of the highest position deciding circuit which are set at '1' and form a selection control part 19 and this detection signal is delivered to a selector 18. The gate of only a single CLR signal line designated by the detection signal is opened and the read signal is sent to the CLR signal line. The designated bit of the register 15 is cleared and the processor performs a prescribed interruption. The processor receives again the signal IRQ when a series of processes are through and reads the register 15. This simplifies the circuit constitution and the operating procedure and attains the effective release of an interruption.
申请公布号 JPS61241856(A) 申请公布日期 1986.10.28
申请号 JP19850083864 申请日期 1985.04.19
申请人 MATSUSHITA GRAPHIC COMMUN SYST INC 发明人 NOMA NOBUHIKO;TAKAGI GENZO
分类号 G06F13/24;G06F9/46;G06F9/48 主分类号 G06F13/24
代理机构 代理人
主权项
地址