发明名称 MANUFACTURE OF COMPLEMENTARY TYPE MIS TRANSISTOR
摘要 PURPOSE:To prevent the lowering of yield due to a disconnection at a stepped section in an Al wiring by simultaneously conducting SiO2 etching before ion implantation for forming a source-drain for an NMOS even in a PMOS section without being limited to a MOS section. CONSTITUTION:SiO2 is grown on a poly Si gate 8 through heat treatment. When boron fore shaping source-drain 7 for a PMOS is implanted successively, boron is hardly intruded into the poly Si gate 8, and is projected sufficiently into an Si substrate 1. A gate oxide film on the source-drain is etched in an extent that the oxide film is removed by using an Hf group etching liquid. A PMOS section is masked with a resist 10, and ions are implanted to form NMOS source-drain 11.
申请公布号 JPS61242063(A) 申请公布日期 1986.10.28
申请号 JP19850083650 申请日期 1985.04.19
申请人 SEIKO INSTR & ELECTRONICS LTD 发明人 KUDO NOBORU
分类号 H01L21/8238;H01L27/092;H01L29/78 主分类号 H01L21/8238
代理机构 代理人
主权项
地址