| 摘要 |
PURPOSE:To obtain the output reference voltage having reduced variance by using an enhancement type MOS transistor and the 1st and 2nd depression type MOS transistors to form a circuit. CONSTITUTION:The (n) channel depression type MOS transistors TR QD1 and QD6 are provided together with an n channel enhancement type MOS TR QE5 and an amplifier 4. The drains of the TR QD1 and the TR QE5 are connected to a power supply terminal 7 via load resistances 2 and 3. The sources and back gates of the TR QD1 and the TR QE5 are connected to the drain of the TR QD6. Then the gate of the TR QD1 and the gate, source and back gate of the TR QD6 are connected to an earth terminal 9. A reverse input terminal (-) and a non-reverse input terminal (+) of the amplifier 4 are connected to the drains of the TR QD1 and the TR QE5 respectively. Then an output terminal of the amplifier 4 and the gate of the TR QE5 are connected to a reference voltage output terminal 8. Thus it is possible to eliminate the variance of the output reference voltage value due to the variance of the threshold voltage values of both TR QD1 and QD6. |
