发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To prevent the generation of undesired interruptions and to shorten the debug processing time by providing a comparison register within a register file and giving operations to the contents of the comparison register and a register to be checked for each step in a debug mode to produce an interruption only when the coincidence is obtained between the contents of both registers. CONSTITUTION:When the debug of software is executed, a programmer sets the register number to be checked to a selection circuit 4 and the value to be compared to a comparison register 2. In addition, the comparison conditions showing the equality, difference, etc. are set to a control circuit 5 respectively. Then a debug mode is set. The circuit 5 is selected in the debug mode by the circuit 4 after execution of each instruction. The operations are given to the contents of the register to be checked and the register 2 through an arithmetic circuit 3. If it is decided from the arithmetic result of the circuit 3 that the conditions are not satisfied, the next instructions is executed. If said conditions are satisfied, the circuit 5 produces an interruption and informs it to the software.
申请公布号 JPS61241844(A) 申请公布日期 1986.10.28
申请号 JP19850083933 申请日期 1985.04.19
申请人 NEC CORP 发明人 HARUI TOSHIROU
分类号 G06F11/28;G06F11/36 主分类号 G06F11/28
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