| 摘要 |
PURPOSE:To control the delay time of a delay circuit by using logical gates which can be set in an active or inactive state for the delay circuit as load gates. CONSTITUTION:The delay circuit consists of a logical gate G1, load gates G2-G4 which are provided with control inputs C2-C4 respectively and enter the inactive state when the control inputs are '0' and the active state when '1', and a load capacitor Cl formed of wiring. The delay time Tpd between the input A and output b of the logical gate G1 is Tpd(G1)+alpha.T(G2)+beta.T(G 3)+gamma.T(G4)+Tcl, where Tpd(G1), T(G2)-T(G4), and Tcl are the delay time of a logical gate G1 oneself, the delay of load gates G2-G4 in active state, and the delay due a load capacity cl, respectively. Therefore, the load gates G2-G4 are placed in the active and inactive states respectively with the control inputs C2-C4 to adjust the delay time Tpd according to the combination of values alpha.beta.gamma. |
