发明名称 |
MULTIPLICATION ACCUMULATOR |
摘要 |
PURPOSE:To decrease the circuit scale of a multiplication accumulator and to reduce greatly the chip size of the circuit when the circuit is converted into an integrated circuit IC, by using a partial product generator and a single stage of an accumulation adder to form an accumulation adder for products. CONSTITUTION:An output 2 of a partial product generator is delivered from a partial product generator 1 for a multiplicand X and a multiplier Y. While an output 4 of an accumulation adder is delivered from an accumulation adder 3 which performs the accumulation addition for the partial production generating output. Thus the accumulation addition value of the product can be obtained just by means of the generator 1 and a single stage of the adder 3 without using an adder for partial products which obtains a partial product through addition. This can reduce the circuit scale of a multiplication accumulator. |
申请公布号 |
JPS61241830(A) |
申请公布日期 |
1986.10.28 |
申请号 |
JP19850082366 |
申请日期 |
1985.04.19 |
申请人 |
HITACHI LTD |
发明人 |
NAKAMURA MASAFUMI;SHIBUYA TOSHIFUMI;ENDO HIROSHI |
分类号 |
G06F7/53;G06F7/533;G06F7/544 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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