| 摘要 |
A decoder circuit for use in a semiconductor member device or the like as a first metal insulator semiconductor field effect transistor (MISFET) acting as a load element, a plurality of parallel-connected MISFETs controlled by the output signals of an address buffer circuit serving as driver signals. Another MISFET is connected between the first MISFET and the parallel-connected MISFETS having a control signal applied to its gate. An output is taken from the junction between the first MISFET and the MISFET connected between the first MISFET and parallel-connected MISFETs. The decoder can generate an output signal regardless of the logic states of the input signals thereto.
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