| 摘要 |
PURPOSE:To shorten the stabilizing time of a clock frequency for reproducing a digital signal and the time for securing a phase locked loop by providing a frequency lead-in means consisting of a frequency counter and an operating circuit for differentiating its output. CONSTITUTION:When executing the reproduction processing of a digital signal, first of all, a digital signal (fi) is used as a sampling frequency and the output frequency of a digital phase locked loop circuit DPLL 4 is measured by a frequency counter 8 in a frequency lead-in means 10. Subsequently, the output frequency of the circuit 8 is differentiated by an operating circuit 9 and the inclination of the frequency rise characteristic of the DPLL 4 is obtained, quantized, and outputted to the DPLL 4. In the DPLL 4, in accordance with this input, the larger its value is, the larger the phase step width is set, the pulse width of an output signal (fd) is varied and the frequency lead-in is executed so as to make it with the transmission rate of the signal (fi). In this way, the lead-in time can be shortened and also the stabilizing time of a clock frequency for reproducing the digital signal and the time for securing the phase locked loop can be shortened. |
