| 摘要 |
PURPOSE:To shorten the frequency lead-in time, the stabilizing time of a clock frequency for reproducing a digital signal and a time for securing a phase locked loop by varying the phase step width of a phase locked loop circuit in accordance with the frequency rise characteristic of a reference oscillator. CONSTITUTION:The output frequency (fo) of a crystal oscillator 5 is measured by a frequency counter 8 by using a digital signal (fi) as a sampling frequency. As a result, a sampling period (fot) at the time (t) is differentiated by an arithmetic circuit 9 and an inclination following the time lapse of a frequency rise characteristic of the crystal oscillator 5, namely, a differential value is obtained. Also, this inclination is quantized and outputted as a signal for controlling a digital phase locked loop circuit (DPLL) 4. In the DPLL 4, in accordance with the differential value from the circuit 9, the larger the value is, the larger the phase step width is set, the pulse width of an output signal (fd) is varied as time elapses, and the frequency lead-in is executed so that the frequency (fd) coincides with the transmission rate (fi) of the digital signal. |
