| 摘要 |
PURPOSE:To prevent expansion of the extent of data deforming by prohibiting re-starting of data transmission when dissidence occurrs in the calculated result in comparison with the final logical address stored in an address register. CONSTITUTION:An arithmetic unit AL2 generates a carry signal every time the address passes through a page bundary as the data transfer progresses, and a data transfer control circuit DTC informs the result to a microprogram control part, and stops the transmitting of a memory-request signal. At every generation of the carry signal, an arithmetic unit AL3 calculates a re-start logical address and computes the last logical address from the number of the remaining data. The computation result is compared with the final logical address stored in an address register ADR, to confirm the validity of the re-start logical address computation. If a computation error is detected, the re-starting of the data transfer is prohibited at said detecting.
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