| 摘要 |
PURPOSE:To reduce the chip area of a D-RAM by eliminating a dummy cell by providing with an electrostatic capacity connected between the 1st and 2nd MOSFET and the 1st and 2nd MOSFET one end of each respectively connected to differing bit lines. CONSTITUTION:The memory cell 7 is comprised of the 1st MOSFET 8, one end of which is connected to the bit line BL, the 2nd MOSFET 9 with one end connected to the bit line -BL and an electrostatic capacity 10 connected between MOSFET 8, 9. The GATE of the 1st, 2nd MOSFET 8, 9 is connected to the same work line W1-Wn. The capacity 10 stores piVc charge and the stored date are identified. By the selected wordline W1-Wn, the MOSFET 8, 9 is turned ON and by the electric charge + or -Vc stored in the electrostatic capacity 10, potential difference is generated between the bit lines and the sense amplifier 1 detects the potential difference and reads out the data.
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