| 摘要 |
<p>PURPOSE:To suppress power consumption of the address decoder circuit to low level by minimizing the potential difference between the source-gate of the transistor for loading address decoder circuit at the time of data programming. CONSTITUTION:At the time of reading data, high voltage VP and ordinary voltage VC is impressed on power source terminal 1 of the gate potential switching circuit 10 according to the data programming, and '1', '0' level is applied on the input node 12 mutually connected between the gates of transistors T6, T7. At the time of reading data, grounding potential is applied on the gate of the transistor T1 for loading the address decoder circuit from the output node 11. At the time of data programming an electric potential (VP-VTH5) higher than the grounding potential is applied and the potential difference between the source-gate of the transistor T1 for load use becomes VTH5 which is smaller than usual. The VTH5 herein is the threshold voltage of the transistor T5.</p> |
