| 摘要 |
PURPOSE:To reduce processing load by so forming the titled system that a processor actuates an interruption processing program and executes the read of an interface information only when an interruption request signal is made. CONSTITUTION:When the interface information varies, a dissidence is generated between the input and output in flip-flop circuits FF1-FF4 that correspond to the said variation of the information. The dissidence is detected by a correspondent exclusive OR circuits EOR1-EOR4, and is transmitted to an interruption processing circuit 16 of a central processing unit 11. On receiving the dissidence signal from a comparator circuit 13, the circuit 16 informs an interruption processing signal to the processor 14, and the processing of reading the interface information is executed. At this processing, as the processor 14 reads out the interface information through a read circuit 12, the input and output in the FF1-FF4 become coincident, and the dissidence output is nullified, and the interruption signal also is automatically made invalid.
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