| 摘要 |
PURPOSE:To selectively inhibit memory access, by implementing a busy pattern which can be displayed by means of a memory busy signal composed of plural bits in accordance with the kind of memory access. CONSTITUTION:When memory access information is set in a port 1 from a unit 0, an OPC section indicating the kind of access is decoded by means of a decoder 21 and a bank address section used for busy control is decoded by means of another decoder 22. At the decoder 21 the kind of memory access to be inhibited determined correspondingly to BUSY bits '0' and '1' is decoded. At a decoder 23, an access inhibiting output is inputted in a selection circuit 2 by outputting the BUSY bits '0' and '1' correspondingly to banks (namely, B0-B3) and taking a logic at a checking circuit 24 for B0 (bank 0).
|
