发明名称 DIRECT MEMORY ACCESS CONTROL CIRCUIT
摘要 PURPOSE:To improve the execution efficiency of a microprocessor, by using the 1st bus which is directly connected with the microprocessor in parallel with the 2nd bus when the 2nd bus is used by a DMA device and the 2nd memory device. CONSTITUTION:This bus control circuit 32 of a direct memory access control circuit stops the operation of a microprocessor, when a direct memory access device (DMA device) connected to the 2nd bus 112 performs a data transferring process with the 1st memory device connected to the 1st bus 111. The bus control circuit 32 permits the microprocessor to make operations by using the 1st bus 111, when the DMA device performs a data transfer process with the 2nd memory device connected with the 2nd bus 112.
申请公布号 JPS61239348(A) 申请公布日期 1986.10.24
申请号 JP19850080092 申请日期 1985.04.17
申请人 FUJI XEROX CO LTD 发明人 TAKAHASHI SEIICHI
分类号 G06F13/28 主分类号 G06F13/28
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