| 摘要 |
<p>PURPOSE:To reduce the occupation area of a PLA section by providing pairs of MOSFETs controlled by a pair of input signals of positive-negative logics, one side of which pairs is made enhancement type and the other side depletion type. CONSTITUTION:Between input lines 16 to which a plurality of pairs of logic input signals A, B,..., anti A, anti B,... classified into positive logic and negative logic are introduced and output lines 18 connected to fixed power source lines 12 of L logic level VSS, enhancement type MOSFETs Q1e-Q6e and depletion type MOSFETs Q1d-Q6d are inserted by series connection of each as a pair. The gate of the MOSFET is connected to the input line 16, and the source and drain are connected to the output line 18 via common region or directly or via through hole contacts C1-C3.</p> |
