| 摘要 |
PURPOSE:To attain error correction by providing a delay circuit, a (2n+1)-adic counter inputting a data transfer pulse, a selection gate and a reset pulse generating circuit bringing the counter into the reset state. CONSTITUTION:A transfer clock inputted together with an input data is inputted to transfer memories M1-M6 as a shift pulse. Further, output data of the transfer memories M1-M6 and the input data not delayed, in total 7 data are inputted to a 7-input selection gate 1. The selection gate 1 switches the selection data at each transfer clock input and the switching control is applied in response to the count output of the 7-adic counter 2. The 7-adic counter 2 uses the transfer clock as the counter input and the count operation realizes the reset at each block when the selection of control information is finished. A reset pulse generating circuit 3 inputs the output data of the 6th transfer memory M6 always by 32-bit synchronously with the transfer clock and applies the reset pulse to the 7-adic counter 2 by detecting the input of 16-bit control information in succession to the 16-bit synchronous information.
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