发明名称 FRAME SYNCHRONIZER
摘要 PURPOSE:To prevent the occurrence of the unnatural action even in case of animation by providing a data comparator, a control circuit for writing and reading and a static picture detecting circuit besides a frame memory, a writing address generating device and a reading address generating device. CONSTITUTION:A data comparator 16, an address control circuit 20 for writing or reading for a frame memory 3, and a static picture detecting circuit 40 are provided. Out of respective address data outputted from writing and reading address generating devices 6 and 13, pulses FW and FR to show the MSB bit data as frame information are supplied to the data comparator 16, a difference PC between a writing timing and a reading timing is detected, and supplied to the address control circuit 20. The address control circuit 20 is composed of the first and second address control circuits 20A and 20B, and has a timing interval setting part 23 to set timing intervals Tc and Td. When the starting timing with writing and reading approaches, the interval enters prescribed intervals Tc and Td and the static picture is detected, address generating devices 6 and 13 are controlled and the deletion or rereading of the same frame data is executed.
申请公布号 JPS61238179(A) 申请公布日期 1986.10.23
申请号 JP19850079986 申请日期 1985.04.15
申请人 SONY CORP 发明人 KUBOTA TATSUYA;TAKANASHI KENJI
分类号 H04N5/073;H04N7/01 主分类号 H04N5/073
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