发明名称 PICTURE PROCESSING APPARATUS
摘要 A plurality of picture element data stored in first and second frame memories are transferred in parallel onto first and second shift registers. These two shift registers are then shifted in synchronism with each other, and two sets of picture element data that are successively obtained are operated by an arithmetic circuit, and results of the operation are returned back to the first shift register. When one course of operation of picture is finished, a plurality of operation results stored in the first shift register are transferred in parallel to the original positions of the first frame memory, in order to carry out at high speeds the logic operation between the two pictures.
申请公布号 WO8606188(A1) 申请公布日期 1986.10.23
申请号 WO1986JP00186 申请日期 1986.04.14
申请人 FANUC LTD 发明人 KURAKAKE, MITSUO;OTSUKA, SHOICHI
分类号 G06F7/38;G06T1/20;G06T1/60;G06T3/00;G06T7/00;(IPC1-7):G06F15/66 主分类号 G06F7/38
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