发明名称 SEMICONDUCTOR MEMORY ELEMENT AND MANUFACTURE THEREOF
摘要 PURPOSE:To make an element area remarkably smaller than conventional elements in the same design reference by forming a MIS transistor for control on the upper side of one post and a storage capacitance on the lower side. CONSTITUTION:An N-type impurity-doped layer 103 is shaped to the surface of the lower one part of a columnar-structure side wall, and a junction capacitance is formed between a P-type silicon substrate 101 and a P-type silicon 102 shaped to a form that it is connected electrically to the substrate 101. A MIS capacitance is formed between an insulating film 104 coating at least one part of the surface of said impurity-doped layer 103 and P-type silicon 105. Source-drain electrodes for a MIS transistor for control are constituted by an N-type impurity-doped layer 106 shaped to the top section of columnar structure and 103. Accordingly, even when the cross section of a columnar structure section is reduced, storage capacitance in sufficient magnitude can be acquired by taking size at a larger value in the depth direction of the substrate, the height direction.
申请公布号 JPS61237464(A) 申请公布日期 1986.10.22
申请号 JP19850079656 申请日期 1985.04.15
申请人 NEC CORP 发明人 MORIMOTO MITSUTAKA
分类号 H01L27/10;H01L21/822;H01L21/8242;H01L27/04;H01L27/108;H01L29/78;H01L29/94 主分类号 H01L27/10
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