| 摘要 |
PURPOSE:To prevent reading of erroneous data by a CPU by providing a 1-bit flag to the start and final data of a split transfer data and reading the flag to judge whether the read data from a memory is correct or not. CONSTITUTION:A sequence processing section I and an I/O section II are connected by a serial transmission line 10 to constitute the transfer system of the split data. One-bit flags F1, F2 are assigned to the head of 16 bits of high- order data and low-order data of the split data. 0, 1 are formed alternately in the flags F1, F2 at each transfer of the combined value of data A and B. The flags F1, F2 are read by the CPU1 of the processing section I and in case of flag F1=F2, it is judged that the from value the I/O section II is transferred correctly. In case of flag F1=F2, it is judged that the value from the I/O section II is not correct. The data value is taken as a counter value of a pulse read by a counter module 9 of the I/O section II. |
