| 摘要 |
<p>A data capture logic system to be associated with a VLSI logic array (11) having a plurality of data registers (14, 18, 22) comprises a control register (72) for holding various input data representing control functions for a data capture mode logic, data capture registers (90, 110, 112, 114), each of which is connectable to one of the data registers (14, 18, 22) in the logic array holding a selected operand from the logic array under test and responsive to control function, wherein the data capture registers receive control signals from the control register, and error detection circuits (24, 26, 28) located in the logic array under test to detect errors in operands occurring in the logic array under test.
<??>Registers (31, 32, 33) are responsive to the error detection circuits and are connected to the data capture registers (90, 110, 112, 114) to store data in the data capture registers when an error is detected. An output data capture register (100) is connected to the data capture registers and has a control portion (200-214) and a data operand portion (216, 218, 220) wherein the control portion holds the control signals representative of an indication of the type of data failure which has occurred and wherein the data operand portion controls selected failed data operands received from the data capture registers. </p> |
