| 摘要 |
A digital signal detector utilizing a detected input digital signal derived from a reference square wave and a received pulse train to establish phase and frequency variations between the reference signal and the received signal. The detected signal and the reference signal are coupled to up-down counters wherein overflow counts from preset values are obtained which are representative of the frequency and phase difference between the reference and received signals. These overflow counts are utilized to establish phase and frequency error correction signals which may be coupled to control the reference oscillator to provide frequency and phase lock between the reference and received signals. |
