| 摘要 |
PURPOSE:To prevent the titled process from becoming a state that a common bus remains occupied at the time of an error, by halting the occupancy of the bus, in case when a control storage parity error has been generated before starting Write, and starting a retry based on the contents of a specified register, after a control storage has been reloaded. CONSTITUTION:An output of a control storage address register, an output 51 of a reserve flag, and an output 67 of a save register can be loaded on a data bus 75, therefore, a program of an auxiliary processor can know their contents. When a selection of a control signal is also executed by a decoder 77, and write signal 76 is turned on, a start signal 48, or a control storage write signal 50, or a control storage address register change signal 65 can be turned on, and the program of the auxiliary processor can control these signals. A signal 88, a signal 89, a signal 90, a signal 91, a signal 93, and a signal 61 are set by a bus occupancy request signal, a bus occupancy permitting signal, a read command signal, a write command signal, a response signal, and when a control storage parity error has been generated, respectively. In case when the control storage parity error has been generated in the course of Read-Modify-Write, the bus reserve is released. |
