| 摘要 |
<p>PURPOSE:To improve the capacity of an arithmetic module by inputting two pieces of data parts required for arithmetic from a waiting means, executing complex addition and subtraction, and outputting a result of its arithmetic to the waiting means. CONSTITUTION:Complex data is inputted as a data bus signal to a complex addition/subtraction module CA being in a data bus 71 from a memory MEM, and a result of its arithmetic passes through a reverse route again, is inputted to the memory MEM through a writer W and the calculation is ended. A necessary data signal is fetched from a data bus signal 101 which has been inputted to a bus interface 61, and inputted to a waiting circuit 2 of a complex addition/ subtraction module 1. In the waiting circuit 2, it is awaited that other one piece of data signal is inputted, only a data part DA is sent to a complex adding/subtracting circuit 3, arithmetic is executed in this circuit, and its result becomes a data bus signal 101 through the waiting circuit 2 and the bus interface 61, and is outputted to a data bus.</p> |
