| 摘要 |
PURPOSE:To decrease the source parasitic resistance, by forming a dummy gate pattern of an insulator on the surface of a semiconductor, growth depositing a thick high-concentration semiconductor layer by the MOCVD process with the use of this pattern as a mask, removing the dummy gate pattern and then vapor depositing a true gate electrode. CONSTITUTION:An N-type GaAs operation layer 22 is provided on a (100) face semi-insulating GaAs substrate 21 and a dummy gate pattern 11 is formed such that the length thereof is vertical to the (0-1-1) face. After a high- concentration GaAs layer 12 is growth deposited by the MOCVD process, the dummy gate pattern 11 is removed and a gate metal is vapor deposited. According to this method, a Schottky-barrier-gate-type field effect transistor having a low source parasitic resistance can be readily produced in a self-aligning manner by simple processes and without requiring a heat-resistive gate. |
