| 摘要 |
PURPOSE:To attain a low power consumption with a simple circuit by decreasing the operating current of inverter circuits connected in cascade and the input capacitance value toward the post-stage. CONSTITUTION:The operating current of CMOS inverter circuits N1-N3 constituting comparators connected in cascade as N1>N2>N3 and the capacitance of capacitors C1-C3 is selected as C1>C2>C3. Thus, since the post-stage circuit receives the amplified output DELTAV of the pre-stage circuit in the comparison operation, then no high sensitivity is required, the operating current, in other words, an MOSFET with a small conductance is used and an inverter circuit with a transfer characteristic changed slowly is used. Thus, when the input and output are short-circuited, a through-current flowing to a common potential point and a power voltage are decreased. Since each input capacitance is decreased, even when the current is decreased, since the zero correction time is reduced, the operating speed is not sacrified.
|
