发明名称 BUS CONNECTION SYSTEM
摘要 PURPOSE:To decrease overrun errors and underrun errors caused in a logical device by allowing each logical device to acquire the right of use of bus with the highest priority periodically. CONSTITUTION:A signal line 7 provided with bus highest priority right for controlling the right of use of a bus highest priority control signal line 6 to each logical device on time-division basis is connected to each logical device in addition to the bus highest priority control signal line 6 acquiring the right of use of the bus 4 with highest priority. Thus, only one logical device permitted by a signal from the signal line 7 provided with bus highest right of use providing signal line can transfer a highest priority use request signal to the bus highest priority control signal line 6. In this case, the information on the line 7 is updated cyclicly in response to the number of logical devices connected to the bus 4. That is, each logical device uses the bus highest priority control signal line 6 on time-division basis by using the information on the the signal line 7 provided with bus highest priority right as a time slot.
申请公布号 JPS61235970(A) 申请公布日期 1986.10.21
申请号 JP19850076416 申请日期 1985.04.12
申请人 HITACHI LTD 发明人 MASUDA TAKESHI
分类号 G06F13/362;G06F13/36 主分类号 G06F13/362
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