| 摘要 |
PURPOSE:To improve the transfer speed by dividing secondary address data into two, using remaining bits to decode the data and designating a controller of each stepping motor. CONSTITUTION:In 5 bits b1-b5 of the secondary address stored in a secondary address storage memory 23, the least significant bit b1 is used for a register selection signal for a controller 4 controlling each pulse motor, and the remaining high-order 4 bits b2-b5 are used to generate a chip selection signal selecting the controller 4 by a decoder 1. The high-order 4 bits (b2-b5) of the secondary address are decoded into 16 ways, then 15 control LSIs are selected by assigning the command group of the secondary address comprising 5 bits (b1*-b5).
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