| 摘要 |
PURPOSE:To make the error of a signal synchronizing clock pulse to an input signal smaller, by extracting a signal approximate to a reference signal from plural signal groups of the 1st signal of a fixed frequency and another signal which carries the 1st signal and using the extracted signal as a clock signal. CONSTITUTION:Flip-flops (FF) 5 and 6 are set at the rise of a clock pulse (b) and an inverted clock pulse (c), respectively, and the output signals of the FFs 5 and 6 are inputted in AND gates 8 and 9. At the same time, a signal (F) is inputted in an FF 7. When the rise of the pulse (b) is earlier than that of the pulse (c), output signals (g) and (h) of the FF 7 respectively become 'low' and 'high' and the output signal (i) of the AND gate 8 is outputted as a signal synchronous clock pulse (k). On the contrary, when the rise of the pulse (c) is earlier than the that of the pulse (b), the output signal (j) of the AND circuit 9 is outputted as the clock pulse (k). Thus the one which rises earlier than the other out of the clocks of an input signal (a) is selected. |
