发明名称 INSPECTING METHOD FOR TRANSISTOR ARRAY
摘要 PURPOSE:To implement high speed inspection, by inspecting the performance of each transistor through a capacitor, which is constituted by both electrodes and one main electrode of each transistor. CONSTITUTION:A gate electrode 2 is formed on a substrate 1 comprising glass and the like. A semiconductor layer 4 is formed through an insulating layer 3. On the semiconductor layer 4, doping layers 5 and 5' for ohmic contact are formed. Two main electrodes are evaporated in contact with the doping layers. A drain electrode 7 is connected to a picture element electrode 8, which is formed on the substrate 1. The picture element electrode 8 is in an electrically opened state. On the picture element electrode 8, a surface electrode 10 is formed so as to hold the insulating layer 3 and an insulating layer 9 for protecting the semiconductor layer 4. A TFT is constituted by the gate electrode 2, the insulating layer 3 as the gate insulating film, the semiconductor layer 4, a source electrode 6 and the drain electrode 7. A capacitor is constituted by the picture element electrode 8, the surface electrode 10 and the insulating layers 3 and 9. The performance of each transistor is inspected through said capacitor.
申请公布号 JPS61234541(A) 申请公布日期 1986.10.18
申请号 JP19850075282 申请日期 1985.04.11
申请人 CANON INC 发明人 OSADA YOSHIYUKI;MIZUTOME ATSUSHI
分类号 G01R31/26;G01R31/00;G02F1/13;G09F9/00;H01L21/66;H01L27/10 主分类号 G01R31/26
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