发明名称 CMOS LEVEL DETECTING CIRCUIT
摘要 PURPOSE:To detect a floating state, by connecting two circuits, each of which is composed of a (P)- and (N)-type transistors connected in series through a resistance, between a positive and negative power sources and taking the AND output of the inverting signal of the drain terminal of one circuit and source potential of the other. CONSTITUTION:When an input terminal 1 is set at a floating level, through currents are respectively made to flow to a series circuit of the 1st (P) and (N) channel transistors 11 and 13 and another series circuit of the 2nd (P) and (N) channel transistors 12 and 14, and the potential at the drain terminal 3 of the 1st (N) channel transistor 13 approaches the level of a negative power source VSS. The potential of the source terminal 4 of the 2nd (P) channel transistor 12 approaches the level of a positive power source VDD. Therefore, a two- input AND circuit 18 outputs logic '1' and causes an alarm to be produced.
申请公布号 JPS61234621(A) 申请公布日期 1986.10.18
申请号 JP19850075948 申请日期 1985.04.10
申请人 NEC CORP 发明人 OUCHI YASUNORI
分类号 H01L27/092;H01L21/8238;H01L27/08;H03K19/00;H03K19/0175;H03K19/0948 主分类号 H01L27/092
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