| 摘要 |
PURPOSE:To equalize required write time on a DRAM having an ECC circuit to that having no ECC circuit by constituting a parity data cell array of a memory where data write and read are attained simultaneously through separate systems independently. CONSTITUTION:A check circuit 34 uses a clock phi3 to apply humming decoding to data in a register 28, that is, read data + parity data + write data, generates a syndrome and stores it in a register 30. When column decoders 14, 18 apply bit wire selection in a column address CAj, a column address CAi at preceding write is inputted to a column decoder 20 to apply bit line selection of a cell array 16. The data on a parity data bus 26 is inverted according to the output of the register 30 by an inverting circuit 46 and the result is written on a memory cell at a cross point between the selection bit line and the word line WLi. The syndrome this time is written on the same memory cell of the cell array 16 at the next write.
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