发明名称 DC LEVEL DETECTING CIRCUIT
摘要 PURPOSE:To make a device small in size by using plural sample and hold circuits and an integrating circuit and combining them to detect a DC level superposed onto an AC signal. CONSTITUTION:A detecting circuit is provided with plural sample and hold circuits SH1-SHN which sample and hold the AC signal in every one period,an integrating circuit IN which integrates outputs from circuits SH1-SHN, and a charging and discharging circuit CD which prevents saturation of the circuit IN. The AC signal (input signal) onto which the DC level is superposed is sampled in one period and is held circuits SH1-SHN at prescribed timings. Sample pulses of the first half period and the latter period are taken out at prescribed timings and are added and integrated by the circuit IN, and the DC level is detected in accordance with data of the difference between them. Thus, the detecting circuit is constituted with an integrated circuit and is made small in size.
申请公布号 JPS61233372(A) 申请公布日期 1986.10.17
申请号 JP19850075023 申请日期 1985.04.09
申请人 FUJITSU LTD 发明人 UENO NORIO
分类号 H04Q3/72;G01R19/165 主分类号 H04Q3/72
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