发明名称 COMPLEMENTARY MOS SEMICONDUCTOR DEVICE
摘要 PURPOSE:To obtain a complementary MOS semiconductor device suitable for high speed action by a method wherein the device is made to have the construction in which portions of P-type and N-type diffusion layers are isolated having a fixed distance from a high concentration N-type channel stopper region and a high concentration P-type channel stopper region formed respectively directly under the insulation isolation regions without coming in contact with the insulation isolation regions thereof. CONSTITUTION:P-type diffusion layers 8a connected to a metal wiring 10 acting as an output terminal for the output signal phi2 of an inverter have a construction being separated having a fixed distance R2 from channel stopper regions 3a in an N-well 1, while N-type diffusion layers 7a are also isolated having a fixed distance R1 from channel stopper regions 2a in a P-type silicon substrate 11. Because the P-type diffusion layers and the N-type diffusion layers acting as the output parts of the CMOS inverter circuit are made to have constructions being isolated having fixed distances from the respective channel stopper regions like this, reduction of capacitances at the sides of the diffusion layers can be obtained, and to make the CMOS semiconductor device to act at a high speed can be attained.
申请公布号 JPS61231748(A) 申请公布日期 1986.10.16
申请号 JP19850073914 申请日期 1985.04.08
申请人 NEC CORP 发明人 TSUCHIDA KATSUZO
分类号 H01L27/08;H01L27/092 主分类号 H01L27/08
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